The invention relates to the field of relaxed SiGe platforms for high speed CMOS electronics and high speed analog circuits.
Si CMOS as a platform for digital integrated circuits has progressed predictably through the industry roadmap. The progress is created through device miniaturization, leading to higher performance, greater reliability, and lower cost. However, new bottlenecks in data flow are appearing as the interconnection hierarchy is expanded. Although digital integrated circuits have progressed at unprecedented rates, analog circuitry has hardly progressed at all. Furthermore, it appears that in the near future, serious economic and technological issues will confront the progress of digital integrated circuits.
The digital and communication chip markets need an enhancement to Si CMOS and the maturing roadmap. One promising candidate material that improves digital integrated circuit technology and introduces new analog integrated circuit possibilities is relaxed SiGe material on Si substrates. Relaxed SiGe alloys on Si can have thin layers of Si deposited on them, creating tension in the thin Si layers. Tensile Si layers have many advantageous properties for the basic device in integrated circuits, the metal-oxide field effect transistor (MOSFET). First, placing Si in tension increases the mobility of electrons moving parallel to the surface of the wafer, thus increasing the frequency of operation of the MOSFET and the associated circuit. Second, the band offset between the relaxed SiGe and the tensile Si will confine electrons in the Si layer. Therefore, in an electron channel device (n-channel), the channel can be removed from the surface or xe2x80x98buriedxe2x80x99. This ability to spatially separate the charge carriers from scattering centers such as ionized impurities and the xe2x80x98roughxe2x80x99 oxide interface enables the production of low noise, high performance analog devices and circuits.
A key development in this field was the invention of relaxed SiGe buffers with low threading dislocation densities. The key background inventions in this area are described in U.S. Pat. No. 5,442,205 issued to Brasen et al. and U.S. Pat. No. 6,107,653 issued to Fitzgerald. These patents define the current best methods of fabricating high quality relaxed SiGe.
Novel device structures in research laboratories have been fabricated on early, primitive versions of the relaxed buffer. For example, strained Si, surface channel nMOSFETs have been created that show enhancements of over 60 % in intrinsic gm with electron mobility increases of over 75% (Rim et al, IEDM 98 Tech. Dig. p. 707). Strained Si, buried channel devices demonstrating high transconductance and high mobility have also been fabricated (U. Konig, MRS Symposium Proceedings 533, 3 (1998)). Unfortunately, these devices possess a variety of problems with respect to commercialization. First, the material quality that is generally available is insufficient for practical utilization, since the surface of SiGe on Si becomes very rough as the material is relaxed via dislocation introduction. These dislocations are essential in the growth of relaxed SiGe layers on Si since they compensate for the stress induced by the lattice mismatch between the materials. For more than 10 years, researchers have tried to intrinsically control the surface morphology through epitaxial growth, but since the stress fields from the misfit dislocations affect the growth front, no intrinsic epitaxial solution is possible. The invention describes a method of planarization and regrowth that allows all devices on relaxed SiGe to possess a significantly flatter surface. This reduction in surface roughness increases the yield for fine-line lithography, thus enabling the manufacture of strained Si devices.
A second problem with the strained Si devices made to date is that researchers have been concentrating on devices optimized for very different applications. The surface channel devices have been explored to enhance conventional MOSFET devices, whereas the buried channel devices have been constructed in ways that mimic the buried channel devices previously available only in III-V materials systems, like AlGaAs/GaAs. Recognizing that the Si manufacturing infrastructure needs a materials platform that is compatible with Si, scalable, and capable of being used in the plethora of Si integrated circuit applications, the disclosed invention provides a platform that allows both the enhancement of circuits based on Si CMOS, as well as the fabrication of analog circuits. Thus, high performance analog or digital systems can be designed with this platform. An additional advantage is that both types of circuits can be fabricated in the CMOS process, and therefore a combined, integrated digital/analog system can be designed as a single-chip solution.
With these advanced SiGe material platforms, it is now possible to provide a variety of device and circuit topologies that take advantage of this new materials system. Exemplary embodiments of the invention describe structures and methods to fabricate advanced strained-layer Si devices, and structures and methods to create circuits based on a multiplicity of devices, all fabricated from the same starting material platform. Starting from the same material platform is key to minimizing cost as well as to allowing as many circuit topologies to be built on this platform as possible.
Accordingly, the invention provides a material platform of planarized relaxed SiGe with regrown device layers. The planarization and regrowth strategy allows device layers to have minimal surface roughness as compared to strategies in which device layers are grown without planarization. This planarized and regrown platform is a host for strained Si devices that can possess optimal characteristics for both digital and analog circuits. Structures and processes are described that allow for the fabrication of high performance digital logic or analog circuits, but the same structure can be used to host a combination of digital and analog circuits, forming a single system-on-chip.
In accordance with one embodiment of the invention, there is provided a method of fabricating a semiconductor structure including providing a relaxed Si1xe2x88x92xGex layer on a substrate; planarizing said relaxed Si1xe2x88x92xGex layer; and depositing a device heterostructure on said planarized relaxed Si1xe2x88x92xGex layer including at least one strained layer.